SH7059 Datasheet, PDF (498/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
SSTDR is initialized by a power-on reset, hardware standby mode, and software standby mode. It is not initialized by a
manual reset.
16.3.7 SS Receive Data Register 0 to 3 (SSRDR0 to SSRDR3)
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in
SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 32-bit data length
is selected, SSRDR0 to SSRDR3 are valid. Do not access invalid bits in SSRDR.
When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to SSRDR where it is stored.
After this, SSTRSR is receive-enabled. Since SSTRSR and SSRDR function as a double buffer in this way, continuous
receive operations can be performed. Read SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR is a
read-only register. SSRDR cannot be written to by the CPU.
SSRDR0
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
SSRDR1
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
SSRDR2
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
SSRDR3
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Rev.3.00 Mar. 12, 2008 Page 408 of 948
REJ09B0177-0300