SH7059 Datasheet, PDF (762/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. ROM (SH7058S)
Since a stack area of maximum 128 bytes is used, an area of at least 128 bytes must be saved before setting the SCO
bit to 1.
If an access by the DMAC or AUD occurs during download, operation cannot be guaranteed. Therefore, access by the
DMAC or AUD must not be executed.
(2.4) FKEY is cleared to H'00 for protection.
(2.5) The value of the DPFR parameter must be checked to confirm the download result.
A recommended procedure for confirming the download result is shown below.
• Check the value of the DPFR parameter (one byte of start address of the download destination specified by
FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that
caused download to fail can be investigated by the description below.
• If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address setting of the
download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit (bit 7) in
FTDAR.
• If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit
(bit 1) in the DPFR parameter to ensure that the download program selection and FKEY register setting were
normal, respectively.
(2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is set to the FUBRA
parameter for initialization.
• The current frequency of the CPU clock is set to the FPEFEQ parameter (general register R4). For the settable
range of the FPEFEQ parameter, see section 29.3.2, Clock Timing.
For the settable range of the FPEFEQ parameter, see section 29.3.2, Clock Timing.
When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization
program and initialization is not performed. For details on the frequency setting, see the description in 24.4.3
(2.1) Flash programming/erasing frequency parameter (FPEFEQ).
• The start address in the user branch destination is set to the FUBRA parameter (general register R5).
When the user branch processing is not required, 0 must be set to FUBRA.
When the user branch is executed, the branch destination is executed in flash memory other than the one that is
to be programmed. The area of the on-chip program that is downloaded cannot be set.
The program processing must be returned from the user branch processing by the RTS instruction.
See the description in 24.4.3 (2.2) Flash user branch address setting parameter (FUBRA).
(2.7) Initialization
When a programming program is downloaded, the initialization program is also downloaded to on-chip RAM. There is
an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The
subroutine is called and initialization is executed by using the following steps.
MOV.L #DLTOP+32,R1
; Set entry address to R1
JSR @R1
; Call initialization routine
NOP
• The general registers other than R0 are saved in the initialization program.
• R0 is a return value of the FPFR parameter.
• Since the stack area is used in the initialization program, a stack area of maximum 128 bytes must be reserved
in RAM.
• Interrupts can be accepted during the execution of the initialization program. However, the program storage
area and stack area in on-chip RAM and register values must not be destroyed.
(2.8) The return value of the initialization program, FPFR (general register R0) is judged.
(2.9) FKEY must be set to H'5A and the user MAT must be prepared for programming.
(2.10) The parameter which is required for programming is set.
Rev.3.00 Mar. 12, 2008 Page 672 of 948
REJ09B0177-0300