SH7059 Datasheet, PDF (401/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Sample Setup Procedure for Interval Timer Operation: An example of the setup procedure for interval timer operation
is shown in figure 11.58.
Start
Select counter clock
Set interval
Start counter
1 1. Set the first-stage counter clock ' in prescaler register 1
(PSCR1).
2. Set the ITVE bit to be used in the interval interrupt request
register (ITVRR) to 1. An interrupt request can be sent to the
2 ^{CPU when the corresponding bit changes to 1 in the}
channel 0 free-running counter (TCNT0).
To start A/D converter sampling, set the ITVA bit to be used
in ITVRR to 1.
3. Set bit 0 to 1 in the timer start register (TSTR) to start
3 _TCNT0.
Interrupt request to CPU
or start of A/D sampling
Figure 11.58 Sample Setup Procedure for Interval Timer Operation
Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5 ): An example of the setup procedure for PWM
timer operation (channels 3 to 5 ) is shown in figure 11.59.
Start
Select counter clock 1
Set port-ATU-II connection 2
Set PWM timer
3
Set GR
4
Start count
5
PWM waveform output
1. Set the first-stage counter clock ' in prescaler register 1
(PSCR1), and select the second-stage counter clock " with
the CKSEL bit in the timer control register (TCR). When
selecting an external clock, at the same time select the
external clock edge type with the CKEG bit in TCR.
2. Set the port control registers (PxCRH, PxCRL)
corresponding to the waveform output port to ATU output
compare-match output. Also set the corresponding bit to 1
in the port IO register (PxIOR) to specify the output attribute.
3. Set bit T3PWM–T5PWM in the timer mode register (TMDR)
to PWM mode. When PWM mode is set, the timer operates
in PWM mode irrespective of the timer I/O control register
(TIOR) contents, and general registers (GR3A to GR3D,
GR4A to GR4D, GR5A to GR5D) can be written to.
4. The GR3A–GR3C, GR4A–GR4C, and GR5A–GR5C ATU
general registers are used as duty registers (DTR), and the
GR3D, GR4D, and GR5D ATU general registers as cycle
registers (CYLR). Set the PWM waveform output 0 output
timing in DTR, and the PWM waveform output 1 output
timing in CYLR. Also, if necessary, interrupt requests can be
sent to the CPU at the 0/1 output timing by making a setting
in the timer interrupt enable register (TIER).
5. Set the corresponding bit to 1 in the timer start register
(TSTR) to start the free-running counter (TCNT) for the
relevant channel.
Figure 11.59 Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5)
Rev.3.00 Mar. 12, 2008 Page 311 of 948
REJ09B0177-0300