SH7059 Datasheet, PDF (306/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 0—Input Capture/Compare-Match Flag 3A (IMF3A): Status flag that indicates GR3A input capture or compare-
match. The flag is not set in PWM mode.
Bit 0: IMF3A
0
1
Description
[Clearing condition]
When IMF3A is read while set to 1, then 0 is written to IMF3A
(Initial value)
[Setting conditions]
• When the TCNT3 value is transferred to GR3A by an input capture signal while GR3A is
functioning as an input capture register. However, IMF3A is not set by input capture with
a channel 9 compare match as the trigger
• When TCNT3 = GR3A while GR3A is functioning as an output compare register
Timer Status Registers 6 and 7 (TSR6, TSR7)
TSR6 and TRS7 indicate the channel 6 and 7 free-running counter up-count and down-count status, and cycle register
compare status.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
UDxD
0
R
6
UDxC
0
R
5
UDxB
0
R
Notes: x = 6 or 7
* Only 0 can be written to clear the flag.
4
UDxA
0
R
3
CMFxD
0
R/(W)*
2
CMFxC
0
R/(W)*
1
CMFxB
0
R/(W)*
0
CMFxA
0
R/(W)*
UDxA to UDxD relate to TSR6 only. Bits relating to TSR7 always read 0.
• Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 7—Count-Up/Count-Down Flag 6D (UD6D): Status flag that indicates the TCNT6D count operation.
Bit 7: UD6D
0
1
Description
Free-running counter TCNT6D operates as an up-counter
Free-running counter TCNT6D operates as a down-counter
• Bit 6—Count-Up/Count-Down Flag 6C (UD6C): Status flag that indicates the TCNT6C count operation.
Bit 6: UD6C
0
1
Description
Free-running counter TCNT6C operates as an up-counter
Free-running counter TCNT6C operates as a down-counter
Rev.3.00 Mar. 12, 2008 Page 216 of 948
REJ09B0177-0300