SH7059 Datasheet, PDF (314/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
11.2.6 Timer Interrupt Enable Registers (TIER)
The timer interrupt enable registers (TIER) are 16-bit registers. The ATU-II has 11 TIER registers: one each for channels
0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For details of channel 10, see section 11.2.26,
Channel 10 Registers.
Channel
0
1
2
3
4
5
6
7
8
9
11
Abbreviation
TIER0
TIER1A, TIER1B
TIER2A, TIER2B
TIER3
Function
Controls input capture, and overflow interrupt request enabling/disabling.
Control input capture, compare-match, and overflow interrupt request enabling/disabling.
Controls input capture, compare-match, and overflow interrupt request enabling/disabling.
TIER6
TIER7
TIER8
TIER9
TIER11
Control cycle register compare-match interrupt request enabling/disabling.
Controls down-counter output end (low) interrupt request enabling/disabling.
Controls event counter compare-match interrupt request enabling/disabling.
Controls input capture, compare-match, and overflow interrupt request enabling/disabling.
The TIER registers are 16-bit readable/writable registers that control enabling/disabling of free-running counter (TCNT)
overflow interrupt requests, channel 0 input capture interrupt requests, channel 1 to 5 and 11 general register input
capture/compare-match interrupt requests, channel 6 and 7 compare-match interrupt requests, channel 8 down-counter
output end interrupt requests, and channel 9 event counter compare-match interrupt requests.
Each TIER is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode.
Timer Interrupt Enable Register 0 (TIER0)
TIER0 controls enabling/disabling of channel 0 input capture and overflow interrupt requests.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
OVE0
ICE0D
ICE0C
ICE0B
ICE0A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R/W
R/W
R/W
R/W
• Bits 15 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 4—Overflow Interrupt Enable 0 (OVE0): Enables or disables interrupt requests by the overflow flag (OVF0) in
TSR0 when OVF0 is set to 1.
Bit 4: OVE0
0
1
Description
OVI0 interrupt requested by OVF0 is disabled
OVI0 interrupt requested by OVF0 is enabled
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 224 of 948
REJ09B0177-0300