SH7059 Datasheet, PDF (395/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Internal data bus
H
CPU
Bus
interface
1st write operation
H
Internal buffer
register
Module data
bus
11. Advanced Timer Unit-II (ATU-II)
TCNT0H
TCNT0L
Internal data bus
L
CPU
Bus
interface
2nd write operation
Module
L
Internal buffer ^{H data bus}
register
TCNT0H
Module data bus
TCNT0L
Figure 11.45 Write to TCNT0
11.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access
Timer registers 1, 2, and 3 (TSTR1, TSTR2, TSTR3) are 8-bit registers. As these registers are connected to the CPU via
an internal 16-bit data bus, a simultaneous 32-bit read or write access to TSTR1, TSTR2, and TSTR3 is automatically
divided into two 16-bit accesses.
Figure 11.46 shows a read from TSTR, and figure 11.47 a write to TSTR.
When reading TSTR, in the first read the TSTR1 and TSTR2 (upper 16-bit) value is output to the internal data bus. Then,
in the second read, the TSTR3 (lower 16-bit) value is output to the internal data bus.
When writing to TSTR, in the first write the upper 16 bits are written to TSTR1 and TSTR2. Then, in the second write,
the lower 16 bits are written to TSTR3. Note that, with the above method, in a 32-bit write the write timing is not the
same for TSTR1/TSTR2 and TSTR3.
For information on 8-bit and 16-bit access, see section 11.5.4, 8-Bit or 16-Bit Accessible Registers.
Internal data bus
H
CPU
Bus
interface
1st read operation
Module data bus H
TSTR2
TSTR1
TSTR3
Internal data bus
L
CPU
Bus
interface
2nd read operation
Module data
bus
L
TSTR2
TSTR1
TSTR3
Figure 11.46 Read from TSTR1, TSTR2, and TSTR3
Rev.3.00 Mar. 12, 2008 Page 305 of 948
REJ09B0177-0300