SH7059 Datasheet, PDF (616/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Multi-Trigger A/D Converter (MTAD)
• Bit 0—A/D Compare Match Interrupt Enable A (ADCMExA): Enables or disables the interrupt request by ADCMFxA
when the ADDRxA compare match flag (ADCMFxA) in ADTSR is set to 1.
Bit 0: ADCMExA
0
1
Note: x = 0 or 1.
Description
The interrupt request (ADDIxA) by ADCMFxA is disabled
The interrupt request (ADDIxA) by ADCMFxA is enabled
(Initial value)
19.2.4 A/D Free-Running Counters (ADCNT0 and ADCNT1)
A/D free-running counters 0 and 1 (ADCNT0 and ADCNT1) are 16-bit readable/writable registers that start incrementing
according to the setting of the A/D trigger control registers (ADTCR0 and ADTCR1).
The clock selected by the prescaler (ADTCR0 and ADTCR1) is input to the corresponding counters. ADCNT0 and
ADCNT1 are initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode.
ADCNT0 and ADCNT1 can only be read from or written to in words.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
19.2.5 A/D General Registers A and B (ADGR0A, ADGR0B, ADGR1A, and ADGR1B)
A/D general registers (ADGR0A, ADGR0B, ADGR1A, and ADGR1B) are 16-bit readable/writable registers. Two
registers are provided for each of channels 0 and 1.
The ADGR value is constantly compared with the corresponding free-running counter (ADCNT0 or ADCNT1) value.
When the two values match, the ADCMFxA and ADCMFxB bits in the corresponding A/D trigger status register
(ADTSR) are set to 1, which requests initiation of the multi-trigger A/D conversion. ADGR0A, ADGR0B, ADGR1A, and
ADGR1B can only be read from or written to in words.
ADGR0A, ADGR0B, ADGR1A, and ADGR1B are initialized to H'FFFF by a power-on reset, and in hardware standby
mode and software standby mode.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial Value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.3.00 Mar. 12, 2008 Page 526 of 948
REJ09B0177-0300