SH7059 Datasheet, PDF (198/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. User Break Controller (UBC)
8.5.3 Contention between User Break and Exception Processing
If a user break is set for the fetch of a particular instruction, and exception processing with higher priority than a user
break is in contention and is accepted in the decode stage for that instruction (or the next instruction), user break exception
processing may not be performed after completion of the higher-priority exception service routine (on return by RTE).
Thus, if a user break condition is applied to the branch destination instruction fetch after a branch (BRA, BRAF, BT, BF,
BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE, exception processing), and that branch instruction accepts exception
processing with higher priority than a user break interrupt, user break exception processing is not performed after
completion of the higher-priority exception service routine.
Therefore, a user break condition should not be set for the fetch of the branch destination instruction after a branch.
8.5.4 Break at Non-Delay Branch Instruction Jump Destination
When a branch instruction with no delay slot (including exception processing) jumps to the jump destination instruction
on execution of the branch, a user break will not be generated even if a user break condition has been set for the first jump
destination instruction fetch.
8.5.5 User Break Trigger Output
Information on internal bus condition matches monitored by the UBC is output as UBCTRG. The trigger width can be set
with clock select bits 1 and 0 (CKS1, CKS0) in the user break control register (UBCR).
If a condition matches occurs again during trigger output, the UBCTRG pin continues to output a low level, and outputs a
pulse of the length set in bits CKS1 and CKS0 from the cycle in which the last condition match occurs.
The trigger output conditions differ from those in the case of a user break interrupt when a CPU instruction fetch condition
is satisfied. When a condition occurs in an overrun fetch instruction as described in section 8.5.2, Instruction Fetch at
Branches, a user break interrupt is not requested but a trigger is output from the UBCTRG pin.
In other CPU data accesses and DMAC bus cycles, pulse output is performed under conditions similar to user break
interrupt conditions.
Setting the user break interrupt disable (UBID) bit to 1 in UBCR enables trigger output to be monitored externally without
requesting a user break interrupt.
8.5.6 Module Standby
After a power-on reset the UBC is in the module standby state, in which the clock supply is halted. When using the UBC,
the module standby state must be cleared before making UBC register settings. Module standby is controlled by the
System Control Register 2 (SYSCR2). See section 27.2.3, System Control Register 2 (SYSCR2), for further details.
Rev.3.00 Mar. 12, 2008 Page 108 of 948
REJ09B0177-0300