SH7059 Datasheet, PDF (249/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Direct memory access controller (DMAC) activation
⎯ The DMAC can be activated by a channel 0 input capture interrupt (ICI0A–D)
⎯ The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt (CMI6A–D)
⎯ The DMAC can be activated by a channel 7 cycle register 7 compare-match interrupt (CMI7A–D)
• A/D converter activation
⎯ The A/D converter can be activated by detection of 1 in bits ITVA6–13 of the channel 0 interval interrupt request
registers (ITVRR1, ITVRR2A, ITVRR2B)
Table 11.1 lists the functions of the ATU-II.
Table 11.1 ATU-II Functions
Item
Channel 0
Channel 1
Channel 2
Channels 3–5
Counter
Clock sources Pφ–Pφ/32
configuration
(Pφ–Pφ/32) × (1/2ⁿ )
(n = 0–5)
(Pφ–Pφ/32) × (1/2ⁿ )
(n = 0–5)
(Pφ–Pφ/32) × (1/2ⁿ )
(n = 0–5)
TCLKA, TCLKB, AGCK, TCLKA, TCLKB, AGCK, TCLKA, TCLKB, AGCK,
AGCKM
AGCKM
AGCKM
Counters
TCNT0H, TCNT0L
TCNT1A, TCNT1B
TCNT2A, TCNT2B
TCNT3–5
General registers —
GR1A–H
GR2A–H
GR3A–D, GR4A–D,
GR5A–D
Dedicated input ICR0AH, ICR0AL,
OSBR1
OSBR2
—
capture
ICR0BH, ICR0BL,
ICR0CH, ICR0CL,
ICR0DH, ICR0DL
Dedicated output —
compare
OCR1
OCR2A–2H
—
PWM output —
—
—
Duty: GR3A–C, GR4A–C,
GR5A–C
Cycle: GR3D, GR4D,
GR5D
Input pins
TI0A–D
—
—
—
I/O pins
—
TIO1A–H
TIO2A–H
TIO3A–D, TIO4A–D,
TIO5A–D
Output pins
—
—
—
—
Counter clearing function
—
—
—
O
Interrupt sources
6 sources
9 sources
9 sources
15 sources
Interval × 1,
Dual input capture/
input capture × 4, overflowcompare-match × 8,
×1
overflow × 1
Dual input capture/
compare-match × 8,
overflow × 1*
Dual input capture/
compare-match × 12,
overflow × 3
(* Same vector)
Inter-channel and inter-module
connection signals
A/D converter activation Compare-match signal Compare-match signal Channel 9 compare-
by interval interrupt
trigger output to channel 8 trigger output to channel 8 match signal input to
request, DMAC activation one-shot pulse output one-shot pulse output capture trigger
by input capture interrupt, down-counter
down-counter
(Channel 3 only)
channel 10 compare- _{Channel 10 compare- Channel 10 compare-}
match signal capture
match signal counter clearmatch signal counter clear
trigger input
input
input
Rev.3.00 Mar. 12, 2008 Page 159 of 948
REJ09B0177-0300