SH7059 Datasheet, PDF (601/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. A/D Converter
In scan mode, the t_CONV values given in table 18.4 apply to the first conversion. In the second and subsequent conversions,
t_CONV is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
Table 18.4 A/D Conversion Time (Single Mode)
CKS = 0:
fop = 10 to 20 MHz
Item
Symbol Min Typ Max
A/D conversion start delay time t
D
10
—
17
Input sampling time
t_SPL
—
64
—
A/D conversion time
t_CONV
259 —
266
CKS = 1:
fop = 10 MHz
Min Typ Max
6
—
9
—
32
—
131 —
134
Unit
States(CK base)
CK
Address
Internal write
signal
Analog input
sampling signal
A/D converter
A/D conversion time (t_CONV)
A/D conversion start
delay time (t_D)
Analog input
sampling time
(t_SPL)
Write cycle
A/D synchronization time
(3 states) (up to 14 states)
ADST write timing
Idle
Sample-and-hold A/D conversion
ADF
Figure 18.6 A/D Conversion Timing
End of A/D
conversion
18.4.4 External Triggering of A/D Conversion
A/D conversion can be externally triggered. To activate the A/D converter with an external trigger, first set the pin
functions with the PFC (pin function controller) and the TRGE bit to 1 in the A/D control register (ADCR), and set the
EXTRG bit to 1 in the A/D trigger register (ADTRGR). When a low level is input to the ADTRG pin after these settings
have been made, the A/D converter detects the falling edge of a pulse and sets the ADST bit to 1. Figure 18.7 shows the
timing for external trigger input.
The ADST bit is set to 1 two states after the A/D converter samples the falling edge on the ADTRG pin. The timing from
setting of the ADST bit until the start of A/D conversion is the same as when 1 is written into the ADST bit by software.
Rev.3.00 Mar. 12, 2008 Page 511 of 948
REJ09B0177-0300