SH7059 Datasheet, PDF (646/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. High-performance User Debug Interface (H-UDI)
20.4 Operation
20.4.1 TAP Controller
Figure 20.2 shows the internal states of the TAP controller. State transitions basically conform with the IEEE1149.1
standard.
1 Test-logic-reset
0
1
0 Run-test/idle
1
Select-DR-scan
1
Capture-DR
0
Shift-DR 0
1
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
10
1
Select-IR-scan
0
1
Capture-IR
0
Shift-IR 0
1
1
Exit1-IR
0
Pause-IR 0
1
0
Exit2-IR
1
Update-IR
10
Figure 20.2 TAP Controller State Transitions
20.4.2 H-UDI Interrupt and Serial Transfer
When an H-UDI interrupt instruction is transferred to SDIR via TDI, an interrupt is generated. Data transfer can be
controlled by means of the H-UDI interrupt service routine. Transfer can be performed by means of SDDR.
Control of data input/output between an external device and the H-UDI is performed by monitoring the SDTRF bit in
SDSR externally and internally. Internal SDTRF bit monitoring is carried out by having SDSR read by the CPU.
The H-UDI interrupt and serial transfer procedure is as follows.
1. An instruction is input to SDIR by serial transfer, and an H-UDI interrupt request is generated.
2. After the H-UDI interrupt request is issued, the SDTRF bit in SDSR is monitored externally. After output of SDTRF =
1 from TDO is observed, serial data is transferred to SDDR.
3. On completion of the serial transfer to SDDR, the SDTRF bit is cleared to 0, and SDDR can be accessed by the CPU.
After SDDR has been accessed, SDDR serial transfer is enabled by setting the SDTRF bit to 1 in SDSR.
4. Serial data transfer between an external device and the H-UDI can be carried out by constantly monitoring the SDTRF
bit in SDSR externally and internally.
Rev.3.00 Mar. 12, 2008 Page 556 of 948
REJ09B0177-0300