SH7059 Datasheet, PDF (596/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. A/D Converter
18.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode
and scan mode. There are two kinds of scan mode: continuous and single-cycle. In single mode, conversion is performed
once on one specified channel, then ends. In continuous scan mode, A/D conversion continues on one or more specified
channels until the ADST bit is cleared to 0. In single-cycle scan mode, A/D conversion ends after being performed once
on one or more channels.
18.4.1 Single Mode
Single mode, should be selected when only one A/D conversion on one channel is required. Single mode is selected by
setting the ADM1 and ADM0 bits in the A/D control/status register (ADSCR) to 00. When the ADST bit in the A/D
control register (ADCR) is set to 1, A/D conversion is started in single mode.
The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends.
When conversion ends, the ADF flag in ADCSR is set to 1. If the ADIE bit in ADCSR is also 1, an ADI interrupt is
requested. To clear the ADF flag, first read ADF when set to 1, then write 0 to ADF. If the DMAC is activated by the ADI
interrupt, ADF is cleared automatically.
An example of the operation when analog input channel 1 (AN1) is selected and A/D conversion is performed in single
mode is described next. Figure 18.3 shows a timing diagram for this example.
1. Single mode is selected (ADM1 = ADM0 = 0), input channel AN1 is selected (CH3 = CH2 = CH1 = 0, CH0 = 1), the
A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred to ADDR1. At the same time the ADF flag is set to 1, the
ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine is started.
5. The routine reads ADF set to 1, then writes 0 to ADF.
6. The routine reads and processes the conversion result (ADDR1).
7. Execution of the A/D interrupt handling routine ends. After this, if the ADST bit is set to 1, A/D conversion starts
again and steps 2 to 7 are repeated.
Rev.3.00 Mar. 12, 2008 Page 506 of 948
REJ09B0177-0300