SH7059 Datasheet, PDF (216/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
This LSI
BREQ accepted
BREQ = Low
External device
Bus right request
Strobe pin:
high-level output
Address, data,
strobe pin:
high impedance
Bus right release
response
BACK confirmation
BACK = Low
Bus right release status
Bus right acquisition
Figure 9.9 Bus Right Release Procedure
9.6 Memory Connection Examples
Figures 9.10–9.13 show examples of the memory connections.
This LSI
CSn
RD
A0–A14
D0–D7
32 K × 8-bit
ROM
CE
OE
A0–A14
I/O0–I/O7
Figure 9.10 Example of 8-Bit Data Bus Width ROM Connection
This LSI
CSn
RD
A0
A1–A18
D0–D15
256 K × 16-bit
ROM
CE
OE
A0–A17
I/O0–I/O15
Figure 9.11 Example of 16-Bit Data Bus Width ROM Connection
Rev.3.00 Mar. 12, 2008 Page 126 of 948
REJ09B0177-0300