SH7059 Datasheet, PDF (509/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
16.5 Interrupt Requests
The SSU interrupt requests consist of transmit data register empty, transmit end, receive data register full, overrun error,
and conflict error. Of these interrupt sources, transmit data register empty, transmit end, receive data register full can
activate the DTC for data transfer.
Since both the overrun error and conflict error interrupt requests are allocated to the SSERI vector address and both the
transmit data empty and transmit end interrupt requests are allocated to the SSTXI vector address, flags should be checked
to decide the interrupt source. Table 16.6 lists interrupt sources.
When an interrupt condition shown in table 16.6 is satisfied, an interrupt requests occur. Clear the interrupt source by the
CPU or a DMAC transfer.
Table 16.6 Interrupt Souses
Channel Abbreviation
0
SSERI0
SSRXI0
SSTXI0
1
SSERI1
SSRXI1
SSTXI1
Legend:
O: Enabled
—: Disabled
Interrupt Request
Overrun error
Conflict error
Receive data register full
Transmit data register empty
Transmit end
Overrun error
Conflict error
Receive data register full
Transmit data register empty
Transmit end
Symbol
OEI0
CEI0
RXI0
TXI0
TEI0
OEI1
CEI1
RXI1
TXI1
TEI1
Interrupt Condition
(RIE = 1) • (ORER = 1)
(CEIE = 1) • (CE = 1)
(RIE = 1) • (RDRF = 1)
(TIE = 1) • (TDRE = 1)
(TEIE = 1) • (TEND = 1)
(RIE = 1) • (ORER = 1)
(CEIE = 1) • (CE = 1)
(RIE = 1) • (RDRF = 1)
(TIE = 1) • (TDRE = 1)
(TEIE = 1) • (TEND = 1)
DMAC Activation
—
—
O
O
O
—
—
O
O
O
16.6 Usage Note
16.6.1 Note on Using the SSU
The LSI's SSU cannot be used as a slave or multi master.
16.6.2 Point to Note when Setting Pins
Although each of SCS0, SCS1, and SSCK1 is assignable to multiple pins, only one pin should be assigned for use by each
signal.
Rev.3.00 Mar. 12, 2008 Page 419 of 948
REJ09B0177-0300