SH7059 Datasheet, PDF (209/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
9.2.4 RAM Emulation Register (RAMER)
• SH7058S
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
RAMS
RAM2
RAM1
RAM0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R/W
R/W
R/W
R/W
The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM area to be used when
emulating realtime programming of flash memory.
RAMER is initialized to H'0000 by a power-on reset, in hardware standby mode, and in software standby mode. It is not
initialized by a manual reset.
Note: To ensure correct operation of the RAM emulation function, the ROM for which RAM emulation is performed
should not be accessed immediately after this register has been modified. Operation cannot be guaranteed if such
an access is made.
• Bits 15 to 4—Reserved: Only 0 should be written to these bits. Operation cannot be guaranteed if 1 is written.
• Bit 3—RAM Select (RAMS): Used together with bits 2 to 0 to select or deselect flash memory emulation by RAM
(table 9.6).
When 1 is written to this bit, all flash memory blocks are write/erase-protected.
This bit is ignored in modes with on-chip ROM disabled.
• Bits 2 to 0—RAM Area Specification (RAM2 to RAM0): These bits are used together with the RAMS bit to designate
the flash memory area to be overlapped onto RAM (table 9.6).
Table 9.6 RAM Area Setting Method (SH7058S)
RAM Area
H'FFFF0000 to H'FFFF0FFF
H'00000000 to H'00000FFF
H'00001000 to H'00001FFF
H'00002000 to H'00002FFF
H'00003000 to H'00003FFF
H'00004000 to H'00004FFF
H'00005000 to H'00005FFF
H'00006000 to H'00006FFF
H'00007000 to H'00007FFF
Legend: *: Don't care
Bit 3: RAMS
0
1
1
1
1
1
1
1
1
Bit 2: RAM2
*
0
0
0
0
1
1
1
1
Bit 1: RAM1
*
0
0
1
1
0
0
1
1
Bit 0: RAM0
*
0
1
0
1
0
1
0
1
Rev.3.00 Mar. 12, 2008 Page 119 of 948
REJ09B0177-0300