SH7059 Datasheet, PDF (907/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27.2.3 System Control Register 2 (SYSCR2)
Bit: 7
6
5
—
—
—
Initial value: 0
0
0
R/W: R
R
R
27. Power-Down State
4
3
2
1
0
— MSTOP3 MSTOP2 MSTOP1 MSTOP0
0
0
0
0
1
R
R/W
R/W
R/W
R/W
System control register 2 (SYSCR2) is an 8-bit readable/writable register that controls the standby state of the AUD, H-
UDI, FPU, and UBC on-chip modules.
SYSCR2 is initialized to H'01 by a power-on reset.
Note: The method of writing to SYSCR2 is different from that of ordinary registers to prevent inadvertent rewriting. See
section 27.2.4, Notes on Register Access, for more information.
• Bit 7⎯Reserved: This bit is always read as 0 and cannot be modified.
• Bits 6 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 3—Module Stop 3 (MSTOP3): Specifies halting of the clock supply to the AUD on-chip peripheral module.
Setting the MSTOP3 bit to 1 stops the clock supply to the AUD. To cancel halting of the clock supply to the AUD,
first set the AUD software reset bit (AUDSRST) in the system control register 1 (SYSCR1) to the AUD reset state
value. Use of the AUD will then be enabled by clearing the AUD reset.
Bit 3: MSTOP3
0
1
Description
AUD operates
Clock supply to AUD stopped
(Initial value)
• Bit 2—Module Stop 2 (MSTOP2): Specifies halting of the clock supply to the H-UDI on-chip peripheral module.
Setting the MSTOP2 bit to 1 stops the clock supply to the H-UDI.
Bit 2: MSTOP2
0
1
Description
H-UDI operates
Clock supply to H-UDI stopped
(Initial value)
• Bit 1—Module Stop 1 (MSTOP1): Specifies halting of the clock supply to the FPU on-chip peripheral module. Setting
the MSTOP1 bit to 1 stops the clock supply to the FPU.
The MSTOP1 bit cannot be cleared by writing 0 after it has been set to 1. In other words, once the MSTOP1 bit has
been set to 1 and the clock supply to the FPU has been stopped, the clock supply to the FPU cannot be resumed by
clearing the MSTOP1 bit to 0.
This LSI's power-on reset is necessary to restart the FPU clock supply after it has been stopped.
Bit 1: MSTOP1
0
1
Description
FPU operates
Clock supply to FPU stopped
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 817 of 948
REJ09B0177-0300