SH7059 Datasheet, PDF (434/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Watchdog Timer (WDT)
13.4.4 System Reset by WDTOVF Signal
If a WDTOVF signal is input to the RES pin, the chip cannot be initialized correctly. Avoid logical input of the WDTOVF
output signal to the RES input pin.
To reset the entire system with the WDTOVF signal, use the circuit shown in figure 13.9.
Reset input
This LSI
RES
Reset signal to
entire system
WDTOVF
Figure 13.9 Example of System Reset Circuit Using WDTOVF Signal
13.4.5 Internal Reset in Watchdog Timer Mode
If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a TCNT overflow
occurs, but TCNT and TCSR in the WDT will be reset.
Because the internal clock obtained by dividing the system clock(φ) is also reset at this time, the SCI, A/D converter, and
CMT that use the internal clock may not operate correctly from hereafter. To continue using these modules, initialize them
before use.
13.4.6 Manual Reset in Watchdog Timer
When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits until the end of the bus
cycle at the time of manual reset generation before making the transition to manual reset exception processing. Therefore,
the bus cycle is retained in a manual reset, but if a manual reset occurs while the bus is released or during DMAC burst
transfer, manual reset exception processing will be deferred until the CPU acquires the bus. However, if the interval from
generation of the manual reset until the CPU acquires the bus cycle is equal to or longer than the internal manual reset
interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception
processing is not executed.
Rev.3.00 Mar. 12, 2008 Page 344 of 948
REJ09B0177-0300