SH7059 Datasheet, PDF (125/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
2.3.3 Instruction Format
Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand
depends on the instruction code. The symbols used are as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9 Instruction Formats
Instruction Formats
0 format
15
xxxx xxxx xxxx
0
xxxx
n format
15
xxxx nnnn
0
xxxx xxxx
m format
15
xxxx mmmm xxxx
0
xxxx
nm format
15
0
xxxx nnnn mmmm xxxx
md format
15
0
xxxx xxxx mmmm dddd
Source
Operand
—
Destination
Operand
—
Example
NOP
—
Control register or system
register
Control register or system
register
mmmm: Direct register
mmmm: Indirect post-
increment register
mmmm: Direct register
mmmm: PC relative using
Rm
mmmm: Direct register
mmmm: Direct register
mmmm: Indirect post-
increment register (multiply-
and-accumulate)
nnnn*: Indirect post-
increment register (multiply-
and-accumulate)
mmmm: Indirect post-
increment register
mmmm: Direct register
mmmm: Direct register
mmmmdddd: Indirect
register with displacement
nnnn: Direct register
nnnn: Direct register
nnnn: Indirect pre-
decrement register
Control register or
system register
Control register or
system register
—
—
nnnn: Direct register
nnnn: Indirect register
MACH, MACL
nnnn: Direct register
nnnn: Indirect pre-
decrement register
nnnn: Indirect indexed
register
R0 (Direct register)
MOVT Rn
STS MACH,Rn
STC.L SR,@-Rn
LDC Rm,SR
LDC.L @Rm+,SR
JMP @Rm
BRAF Rm
ADD
MOV.L
MAC.W
Rm,Rn
Rm,@Rn
@Rm+,@Rn+
MOV.L @Rm+,Rn
MOV.L Rm,@-Rn
MOV.L Rm,@(R0,Rn)
MOV.B @(disp,Rn),R0
Rev.3.00 Mar. 12, 2008 Page 35 of 948
REJ09B0177-0300