SH7059 Datasheet, PDF (411/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Contention between DCNT Write and Counter Clearing by Underflow: If an underflow occurs in the T2 state of the
channel 8 down-counter (DCNT8A to DCNT8P) write cycle by the CPU and the DCNT is stopped, the retention of the
H’0000 value has priority and the write to the DCNT by the CPU is not performed. Setting the status flag (OSF) to 1 at the
underflow timing is performed in the same way as for a normal underflow.
The timing in this case is shown in figure 11.72. In this example, a write of H'5555 to DCNT is attempted at the same time
as DCNT underflows.
Note:
In the SH7055, a write to DCNT from the CPU is not attempted, but retention of H’0000 takes precedence. Note
that its operation is different.
T1
T2
Pφ
DCNT input clock
Address
DCNT address
Write data
5555
Internal write signal
Underflow signal
H'5555 is written due to the DCNT write priority
DCNT 0001
0000
5555
Interrupt status flag
(OSF)
Figure 11.72 Contention between DCNT Write and Underflow
Rev.3.00 Mar. 12, 2008 Page 321 of 948
REJ09B0177-0300