SH7059 Datasheet, PDF (156/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Exception Processing
6.1.2 Exception Processing Operations
The exception processing sources are detected and begin processing according to the timing shown in table 6.2.
Table 6.2 Timing of Exception Source Detection and Start of Exception Processing
Exception Source
Reset
Power-on reset
Manual reset
Address error
Interrupts
Instructions
Trap instruction
General illegal
instructions
Illegal slot instructions
Floating point
instructions
Timing of Source Detection and Start of Processing
Starts when the RES pin changes from low to high or when the WDT overflows.
Starts when the WDT overflows.
Detected when instruction is decoded and starts when the previous executing
instruction finishes executing.
Detected when instruction is decoded and starts when the previous executing
instruction finishes executing.
Starts from the execution of a TRAPA instruction.
Starts from the decoding of undefined code anytime except after a delayed
branch instruction (delay slot).
Starts from the decoding of undefined code placed in a delayed branch instruction
(delay slot) or of instructions that rewrite the PC.
Starts when a floating-point instruction causes an invalid operation exception
(IEEE754 specification) or division-by-zero exception.
When exception processing starts, the CPU operates as follows:
1. Exception processing triggered by reset:
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector
table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008
and H'0000000C addresses for manual resets). See section 6.1.3, Exception Processing Vector Table, for more
information. H'00000000 is then written to the vector base register (VBR) and H'F (1111) is written to the interrupt
mask bits (I3–I0) of the status register (SR). The program begins running from the PC address fetched from the
exception processing vector table.
2. Exception processing triggered by address errors, interrupts and instructions:
SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is
written to the SR's interrupt mask bits (I3–I0). For address error and instruction exception processing, the I3–I0 bits are
not affected. The start address is then fetched from the exception processing vector table and the program begins
running from that address.
6.1.3 Exception Processing Vector Table
Before exception processing begins running, the exception processing vector table must be set in memory. The exception
processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds
the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets, from which the vector table
addresses are calculated. During exception processing, the start addresses of the exception service routines are fetched
from the exception processing vector table, which is indicated by this vector table address.
Table 6.3 shows the vector numbers and vector table address offsets. Table 6.4 shows how vector table addresses are
calculated.
Rev.3.00 Mar. 12, 2008 Page 66 of 948
REJ09B0177-0300