SH7059 Datasheet, PDF (150/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Clock Pulse Generator (CPG)
5.1.2 Pin Configuration
The pins relating to the clock pulse generator are shown in table 5.1.
Table 5.1 CPG Pins
Pin Name
External clock
Crystal
System clock
PLL power supply
PLL ground
PLL capacitance
Abbreviation
EXTAL
XTAL
CK
PLLV_CC
PLLV_SS
PLLCAP
I/O
Input
Input/output
Output
Input
Input
Input
Description
Crystal oscillator or external clock input
Crystal oscillator connection
System clock output
PLL multiplier circuit power supply
PLL multiplier circuit ground
PLL multiplier circuit oscillation external
capacitance pin
5.2 Frequency Ranges
5.2.1 Frequency Ranges
The input frequency and operating frequency ranges are shown in table 5.2.
Table 5.2 Input Frequency and Operating Frequency
Input Frequency
Range (MHz)
PLL Multiplication
Factor
Internal Clock (φ)
Frequency Range
(MHz)
5 to 10
×8
40 to 80
Note: Crystal oscillator and external clock input
Peripheral Clock (Pφ) System Clock
Frequency Range
Frequency Range
(MHz)
(MHz)
10 to 20
10 to 20
Two types of clock signals, internal clock (φ) and peripheral clock (Pφ) signals, are supplied and used by this LSI.
The internal clock signal (φ), with frequency eight times the frequency of the clock signal input from the EXTAL pin, is
mainly supplied to the bus master modules such as CPU, FPU, and DMAC.
The peripheral clock signal (Pφ), with frequency two times the frequency of the clock signal input from the EXTAL pin, is
mainly supplied to the on-chip peripheral modules. The CK pin outputs the peripheral clock signal (Pφ) signal as the
system clock signal.
Rev.3.00 Mar. 12, 2008 Page 60 of 948
REJ09B0177-0300