SH7059 Datasheet, PDF (845/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

25. ROM (SH7059)
The details of the programming procedure are described below. The procedure program must be executed in an area
other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for
downloading must be executed in the on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external
space) is shown in section 25.10.3, Storable Area for Procedure Program and Programming Data.
The following description assumes the area to be programmed on the user MAT is erased and program data is prepared
in the consecutive area. When erasing has not been executed, carry out erasing before writing.
128-byte programming is performed in one program processing. When more than 128-byte programming is performed,
programming destination address/program data parameter is updated in 128-byte units and programming is repeated.
When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the invalid
data to be added is H'FF, the program processing period can be shortened.
(2.1) Select the on-chip program to be downloaded
When the PPVS bit of FPCS is set to 1, the programming program is selected.
Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not
performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter.
Specify the start address of the download destination by FTDAR.
(2.2) Write H'A5 in FKEY
If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for a download request.
(2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed.
VBR must always be cleared to H'00000000 before setting the SCO bit to 1.
To write 1 to the SCO bit, the following conditions must be satisfied.
• RAM emulation mode is canceled.
• H'A5 is written to FKEY.
• The SCO bit writing is executed in the on-chip RAM.
When the SCO bit is set to 1, download is started automatically. When execution returns to the user procedure
program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure
program.
The download result can be confirmed only by the return value of the DPFR parameter. Before the SCO bit is set to 1,
incorrect judgement must be prevented by setting the DPFR parameter, that is one byte of the start address of the on-
chip RAM area specified by FTDAR, to a value other than the return value (H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank switch as described
below, is performed as an internal microcomputer processing, so VBR need to be cleared to 0. Eight NOP instructions
are executed immediately after the instructions that set the SCO bit to 1.
• The user MAT space is switched to the on-chip program storage area.
• After the selection condition of the download program and the address set in FTDAR are checked, the transfer
processing is executed starting from the on-chip RAM address specified by FTDAR.
• The SCO bits in FPCS, FECS, and FCCS are cleared to 0.
• The return value is set to the DPFR parameter.
• After the on-chip program storage area is returned to the user MAT space, execution returns to the user
procedure program.
After download is completed and the user procedure program is running, the VBR setting can be changed.
The notes on download are as follows.
In the download processing, the values of the general registers of the CPU are retained.
During the download processing, the interrupt processing cannot be executed. However, the NMI, UBC, and H-UDI
interrupt requests are retained, so that on returning to the user procedure program, the interrupt processing starts. For
details on the relationship between download and interrupts, see section 25.8.2, Interrupts during
Programming/Erasing.
Rev.3.00 Mar. 12, 2008 Page 755 of 948
REJ09B0177-0300