SH7059 Datasheet, PDF (558/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Bit
15 to 0
Bit Name Initial Value R/W
TDCR[15:0] 0
R/W
Description
Timer Drift Correction Register
Set the value of the cycle to adjust the drift of the timer.
Important: For a proper operation of the timer, the maximum value must be
TDCR <= 8000 (hexadecimal).
17.6.6 Local Offset Register n (LOSRn) (n = 0, 1)
The local offset register (LOSR) is a 16-bit readable/writable register that sets a local offset value to TCNTR. When
TCNTR is cleared by an overflow, timer compare match, or CAN-ID compare match, TCNTR starts running at the value
set in this register.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOSR[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0
Bit Name Initial Value R/W
LOSR[15:0] 0
R/W
Description
Local Offset Register
Indicate the value of the local offset for TCNTR to start with.
17.6.7 Cycle Counter Register n (CCRn) (n = 0, 1)
The cycle counter register (CCR) is a 4-bit readable/writable register that stores the number of the basic cycles for time
triggered transmission. Its value is incremented by one every time the free-running counter (TCNTR) is cleared to 0 by a
compare match condition on TCMR0.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR[3:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Bit
15 to 4
3 to 0
Bit Name
—
CCR[3:0]
Initial Value R/W
0
R
0
R/W
Description
Reserved
Cycle Counter
Indicate the number of the current basic cycles of the matrix cycle for timer
triggered transmission.
Rev.3.00 Mar. 12, 2008 Page 468 of 948
REJ09B0177-0300