SH7059 Datasheet, PDF (408/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Contention between Interrupt Status Flag Setting by Interrupt Generation and Clearing: If an event such as input
capture/compare-match or overflow/underflow occurs in the T2 state of an interrupt status flag 0 write cycle by the CPU,
clearing by the 0 write has priority and the interrupt status flag is cleared.
The timing in this case is shown in figure 11.67.
TSR write cycle
T1
T2
P
Address
Internal write signal
TCNT
TSR address
0 written
to TSR
N
N+1
GR
N
Compare-match signal
Interrupt status flag
IMF
Figure 11.67 Contention between Interrupt Status Flag Setting by Compare-Match and Clearing
Contention between DTR Write and BFR Value transfer by Buffer Function: In channels 6 and 7, if there is
contention between transfer of the buffer register (BFR) value to the corresponding duty register (DTR) due to a cycle
register (CYLR) compare-match, and a write to DTR by the CPU, the CPU write value is written to DTR.
Figure 11.68 shows an example in which contention arises when the BFR value is H'AAAA and the value to be written to
DTR is H'5555.
P
Address
Internal write signal
Compare-match signal
DTR address
H'5555
written
to DTR
BFR
H'AAAA
DTR
H'5555
Figure 11.68 Contention between DTR Write and BFR Value Transfer by Buffer Function
Rev.3.00 Mar. 12, 2008 Page 318 of 948
REJ09B0177-0300