SH7059 Datasheet, PDF (756/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. ROM (SH7058S)
24.5 On-Board Programming Mode
When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that
can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user
programming mode, user boot mode, and boot mode.
For details on the pin setting for entering each mode, see table 24.1. For details on the state transition of each mode for
flash memory, see figure 24.2.
24.5.1 Boot Mode
Boot mode executes programming/erasing user MAT and user boot MAT by means of the control command and program
data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data
must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed
after this LSI's pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate is
automatically adjusted, the communication with the host is executed by means of the control command method. The RAM
areas used by boot mode are 3 Kbytes starting at address H'FFFF0000, 4 Kbytes starting at address H'FFFFB000, and 128
bytes from H'FFFFBF80 to H'FFFFBFFF, which are used as the stack.
The system configuration diagram in boot mode is shown in figure 24.6. For details on the pin setting in boot mode, see
table 24.1. Interrupts are ignored in boot mode, so do not generate them. Note that the AUD cannot be used during boot
mode operation.
This LSI
Host
Boot
programming
tool and program
data
Control command, program data
Reply response
Control command,
analysis execution
software (on-chip)
RxD1
On-chip SCI1
TxD1
Flash
memory
On-chip RAM
Figure 24.6 System Configuration in Boot Mode
(1) SCI Interface Setting by Host
When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00),
which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no
parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits
the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00)
has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot
mode is initiated again (reset) and the operation described above must be executed. The bit rate between the host and
this LSI is not matched because of the bit rate of transmission by the host and system clock frequency of this LSI. To
operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps.
The system clock frequency which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI
is shown in table 24.8. Boot mode must be initiated in the range of this system clock.
Rev.3.00 Mar. 12, 2008 Page 666 of 948
REJ09B0177-0300