SH7059 Datasheet, PDF (374/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
16-bit correction counter 10F (TCNT10F) has Pφ as its input and is constantly compared with 16-bit correction counter
10E (TCNT10E). When the 16-bit correction counter 10F (TCNT10F) value is smaller than that in 16-bit correction
counter 10E (TCNT10E), it is incremented and generates count-up AGCKM. When the 16-bit correction counter 10F
(TCNT10F) value exceeds that in 16-bit correction counter 10E (TCNT10E), no count-up operation is performed. The
TI10 multiplied signal (AGCKM) generated when TCNT10F is incremented is output to the channel 1 to 5 free-
running counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5), and an up-count can be
performed on AGCKM by setting this as the counter clock on each channel. TCNT10F is constantly compared with the
16-bit correction counter clear register (TCCLR10), and when the free-running counter 10F (TCNT10F) and correction
counter clear register (TCCLR10) values match, the TCNT10F up-count stops. Setting TRG1AEN, TRG1BEN,
TRG2AEN, and TRG2BEN in the timer control register (TCR10) enables the channel 1 and 2 free-running counters
(TCNT1A, TCNT1B, TCNT2A, TCNT2B) to be cleared at this time. If TI10 is input when TCNT10D = H'0000,
initialization and correction operations are performed. When TCNT10F = TCCLR10, TCNT10F is cleared to H'0001.
When TCNT10F ≠ TCCLR10, TCNT10F automatically counts up to the TCCLR10 value, and is cleared to H'0001.
Channel 11: Channel 11 has a 16-bit free-running counter (TCNT11) and two 16-bit general registers (GR11A and
GR11B). TCNT11 is an up-counter that performs free-running operation. The counter can generate an interrupt request
when it overflows. The two general registers (GR11A and GR11B) each have a corresponding external signal I/O pin
(TIO11A, TIO11B), and can be used as input capture or output compare registers.
When used for input capture, the free-running counter (TCNT11) value is captured by means of input from the
corresponding external signal I/O pin (TIO11A, TIO11B). Rising edge, falling edge, or both edges can be selected for the
input capture signal in the timer I/O control register (TIOR11). When used for output compare, compare-match with the
free-running counter (TCNT11) is performed. For the output from the external signal I/O pins by compare-match, 0
output, 1 output, or toggle output can be selected in the timer I/O control register (TIOR11). An interrupt can be requested
on the occurrence of the respective input capture or compare-match. When the two general registers (GR11A and GR11B)
are designated for compare-match use, a compare-match signal can be output to the APC.
Prescaler: The ATU-II has a dedicated prescaler with a 2-stage configuration. The first stage comprises 5-bit prescalers
(PSCR1 to PSCR4) that generate a 1/m clock (where m = 1 to 32) with respect to clock Pφ. The second prescaler stage
allows selection of a clock obtained by further scaling the clock from the first stage by 2n (where n = 0 to 5) according to
the timer control registers for the respective channels (TCR1A, TCR1B, TCR2A, TCR2B, TCR3 to TCR5, TCR6A,
TCR6B, TCR7A, TCR7B, TCR8, TCR11).
The prescalers of channels 1 to 8 and 11 have a 2-stage configuration, while the channel 0 and 10 prescalers only have a
first stage. The first-stage prescaler is common to channels 0 to 5, 8, and 11, and it is not possible to set different first-
stage division ratios for each. Channels 6, 7, and 10 each have a first-stage prescaler, and different first-stage division
ratios can be set for each.
11.3.2 Free-Running Counter Operation and Cyclic Counter Operation
The free-running counters (TCNT) in ATU-II channels 0 to 5 and 11 start counting up as free-running counters when the
corresponding timer start register (TSTR) bit is set to 1. When TCNT overflows (channel 0: from H'FFFFFFFF to
H'00000000; channels 1 to 5 and 11: from H'FFFF to H'0000), the OVF bit in the timer status register (TSR) is set to 1. If
the OVE bit in the corresponding timer interrupt enable register (TIER) is set to 1 at this time, an interrupt request is sent
to the CPU. After overflowing, TCNT starts counting up again from H'00000000 or H'0000.
If the TSTR value is cleared to 0 during TCNT operation, the corresponding TCNT halts. In this case, TCNT is not reset.
If external output is being performed from the GR for the corresponding TCNT, the output value does not change.
Channel 0 free-running counter operation is shown in figure 11.13.
Rev.3.00 Mar. 12, 2008 Page 284 of 948
REJ09B0177-0300