SH7059 Datasheet, PDF (149/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Clock Pulse Generator (CPG)
Section 5 Clock Pulse Generator (CPG)
5.1 Overview
The clock pulse generator (CPG) supplies clock pulses inside this LSI chip and to external devices. This LSI CPG consists
of an oscillator circuit and a PLL multiplier circuit. There are two methods of generating a clock with the CPG: by
connecting a crystal resonator, or by inputting an external clock. The oscillator circuit oscillates at the same frequency as
the input clock. Two types of clock signals, internal clock (φ) and peripheral clock (Pφ) signals, are supplied and used by
this LSI. The internal clock signal (φ), with frequency eight times the frequency of the clock signal input from the EXTAL
pin, is mainly supplied to the bus master modules. The peripheral clock signal (Pφ), with frequency two times the
frequency of the clock signal input from the EXTAL pin, is mainly supplied to the on-chip peripheral modules. The CK
pin outputs the peripheral clock signal (Pφ).
The CPG is halted in software standby mode and hardware standby mode.
5.1.1 Block Diagram
A block diagram of the clock pulse generator is shown in figure 5.1.
EXTAL
XTAL
CPG
Oscillator
circuit
PLL multiplier circuit
PLLVcc
PLLVss
PLLcap
CK pin
(System clock)
×2
×8
Peripheral clock (Pφ) Internal clock (φ)
Figure 5.1 Block Diagram of Clock Pulse Generator
Rev.3.00 Mar. 12, 2008 Page 59 of 948
REJ09B0177-0300