SH7059 Datasheet, PDF (92/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1. Overview
Table 1.1 Features
Item
CPU
Operating states
Multiplier
Floating-point unit (FPU)
Features
• Maximum operating frequency: 80 MHz
• Original Renesas SH-2E CPU
• 32-bit internal architecture
• General register machine
⎯ Sixteen 32-bit general registers
⎯ Three 32-bit control registers
⎯ Four 32-bit system registers
• Instruction execution time: Basic instructions execute in one state
(12.5 ns/instruction at 80 MHz operation)
• Address space: Architecture supports 4 Gbytes
• Five-stage pipeline
• Operating modes
⎯ Single-chip mode
⎯ 8/16-bit bus expanded mode
• Mode with on-chip ROM
• Mode with no on-chip ROM
• Processing states
⎯ Reset state
⎯ Program execution state
⎯ Exception handling state
⎯ Bus-released state
⎯ Power-down state
• Power-down state
⎯ Sleep mode
⎯ Software standby mode
⎯ Hardware standby mode
⎯ Module standby
• 32 × 32 → 64 multiply operations executed in two to four cycles
32 × 32 + 64 → 64 multiply-and-accumulate operations executed in two to four cycles
• SuperH architecture coprocessor
• Supports single-precision floating-point operations
• Supports a subset of the data types specified by the IEEE standard
• Supports invalid operation and division-by-zero exception detection (subset of IEEE
standard)
• Supports Round to Zero as the rounding mode (subset of IEEE standard)
• Sixteen 32-bit floating-point data registers
• Supports the FMAC instruction (multiply-and-accumulate instruction)
• Supports the FDIV instruction (divide instruction)
• Supports the FLDI0/FLDI1 instructions (constant 0/1 load instructions)
• Instruction delay time: Two cycles for each of FMAC, FADD, FSUB, and FMUL instructions
• Execution pitch: One cycle for each of FMAC, FADD, FSUB, and FMUL instructions
Rev.3.00 Mar. 12, 2008 Page 2 of 948
REJ09B0177-0300