SH7059 Datasheet, PDF (862/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

25. ROM (SH7059)
3. Interrupt requests generated during download
Even though an interrupt is requested during SCO download, the interrupt processing is not executed until
download ends. Note that interrupt requests are basically retained, so that on completion of download, the interrupt
processing starts. When more than one type of interrupts are requested, their priorities are judged by the interrupt
controller (INTC), and execution starts from the interrupt processing with higher priority.
⎯ NMI, UBC, and H-UDI interrupt requests
When these interrupt requests occur during SCO download, their interrupt sources are retained.
⎯ IRQ interrupt request
Falling-edge detection or low-level detection can be specified for an IRQ interrupt.
• Falling-edge detection is selected: When the falling-edge of IRQ is detected during SCO download, the
interrupt source is retained.
• Low-level detection is selected: When the low-level of IRQ is detected during SCO download, if the IRQ
remains low when download ends, the interrupt processing starts. If the IRQ is high when download ends, the
interrupt source will be canceled.
⎯ On-chip peripheral module interrupt request
An interrupt from an on-chip peripheral module is requested by input of the specified level. Since the interrupt
signal continues to be output unless the interrupt flag is cleared, the interrupt source is retained.
(2) Interrupts during programming/erasing
Though an interrupt processing can be executed at realtime during programming/erasing of the downloaded on-chip
program, the following limitations and notes are applied.
1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed.
Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure
the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory
is read, the read values are not guaranteed. If flash memory that is being programmed or erased is accessed, the
error protect state is entered, and programming or erasing is aborted.
2. Do not rewrite the program data specified by the FMPDR parameter. If new program data is to provided by the
interrupt processing, temporarily save the new program data in another area. After confirming the completion of
programming, save the new program data in the area specified by FMPDR or change the setting in FMPDR to
indicated the other area in which the new program data was temporarily saved.
3. Make sure the interrupt processing routine does not rewrite the contents of the flash-memory related registers or
data in the downloaded on-chip program area. During the interrupt processing, do not simultaneously perform
RAM emulation, download of the on-chip program by an SCO request, or programming/erasing.
4. At the beginning of the interrupt processing routine, save the CPU register contents. Before returning from the
interrupt processing, write the saved contents in the CPU registers again.
5. When a transition is made to sleep mode in the interrupt processing routine, the error protection state is entered and
programming/erasing is aborted.
If a transition is made to the reset state, the reset signal should only be released after providing a reset input over a
period longer than the normal 100 μs to reduce the damage to flash memory.
25.8.3 Other Notes
1. Download time of on-chip program
The programming program that includes the initialization routine and the erasing program that includes the
initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 80 MHz, the download
for each program takes approximately 300 μs at maximum.
2. User branch processing intervals
The intervals for executing the user branch processing differs in programming and erasing. The processing phase also
differs. Table 25.11 lists the minimum and maximum user branch processing intervals when the CPU clock frequency
is 80 MHz.
Rev.3.00 Mar. 12, 2008 Page 772 of 948
REJ09B0177-0300