SH7059 Datasheet, PDF (145/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Floating-Point Unit (FPU)
If a non-number (sNaN) is input in an operation that generates a floating-point value:
• When the EV bit in the FPSCR register is reset, the operation result (output) is a quiet NaN (qNaN).
• When the EV bit in the FPSCR register is set, an invalid operation exception will be generated. In this case, the
contents of the operation destination register do not change.
If a quiet NaN is input in an operation that generates a floating-point value, and a signaling NaN has not been input in that
operation, the output will always be a quiet NaN irrespective of the setting of the EV bit in the FPSCR register. An
exception will not be generated in this case.
Refer to the SH-2E Software Manual for details of floating-point operations when a non-number (NaN) is input.
3.3.3 Denormalized Number Values
For a denormalized number floating-point value, the biased exponent is expressed as 0, the fraction as a non-zero value,
and the hidden bit as 0. In this LSI's floating-point unit, a denormalized number (operand source or operation result) is
always flushed to 0 in a floating-point operation that generates a value (an operation other than copy).
3.3.4 Other Special Values
Floating-point value representations include the seven different kinds of special values shown in table 3.2.
Table 3.2 Representation of Special Values in Single-Precision Floating-Point Operations Specified by IEEE754
Standard
Value
+0.0
–0.0
Denormalized number
+INF
–INF
qNaN (quiet NaN)
sNaN (signaling NaN)
Representation
0x00000000
0x80000000
As described in section 3.3.3, Denormalized Number Values
0x7F800000
0xFF800000
As described in section 3.3.2, Non-Numbers (NaN)
As described in section 3.3.2, Non-Numbers (NaN)
3.4 Floating-Point Exception Model
3.4.1 Enable State Exceptions
Invalid operation and division-by-zero exceptions are both placed in the enable state by setting the enable bit. All
exceptions generated by the FPU are mapped as the same exception event. The meaning of a particular exception is
determined by software by reading system register FPSCR and analyzing the information held there.
3.4.2 Disable State Exceptions
If the EV enable bit is not set, a qNaN will be generated as the result of an invalid operation (except for FCMP and
FTRC). If the EZ enable bit is not set, division-by-zero will return infinity with the sign (+ or –) of the current expression.
Overflow will generate a finite number which is the largest value that can be expressed by an absolute value in the format,
with the correct sign. Underflow will generate zero with the correct sign. If the operation result is inexact, the destination
register will store that inexact result.
Rev.3.00 Mar. 12, 2008 Page 55 of 948
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