SH7059 Datasheet, PDF (397/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
CPU
Internal data bus
Only upper 8 bits used
Bus
interface
Module data bus
Only upper 8 bits used
Figure 11.49 Byte Read/Write Access to TIOR1B
TIOR1B
TIOR1A
CPU
Internal data bus
Only lower 8 bits used
Bus
interface
Module data bus
Only lower 8 bits used
Figure 11.50 Byte Read/Write Access to TIOR1A
TIOR1B
TIOR1A
CPU
Internal data bus
Bus
interface
Module data bus
TIOR1B
TIOR1A
Figure 11.51 Word Read/Write Access to TIOR1A and TIOR1B
11.5.5 Registers Requiring 8-Bit Access
The timer mode register (TMDR), prescaler register (PSCR), timer I/O control registers (TIOR0, TIOR10, TIOR11),
trigger mode register (TRGMDR), interval interrupt request register (ITVRR), timer control registers (TCR3, TCR4,
TCR5, TCR8, TCR9A to TCR9C, TCR10, TCR11), PWM mode register (PMDR), reload enable register (RLDENR),
free-running counters (TCNT10B, TCNT10D, TCNT10H), event counter (ECNT), general registers (GR9A to GR9F),
output compare register (OCR10B), and noise canceler register (NCR) are 8-bit registers. These registers are connected to
the CPU with the upper 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time.
Figure 11.52 shows the operation when performing individual byte read or write accesses to ITVRR1.
CPU
Internal data bus
Only upper 8 bits used
Bus
interface
Module data bus
Only upper 8 bits used
Figure 11.52 Byte Read/Write Access to ITVRR1
ITVRR1
11.6 Sample Setup Procedures
Sample setup procedures for activating the various ATU-II functions are shown below.
Sample Setup Procedure for Input Capture: An example of the setup procedure for input capture is shown in figure
11.53.
Rev.3.00 Mar. 12, 2008 Page 307 of 948
REJ09B0177-0300