SH7059 Datasheet, PDF (321/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 3—Compare-Match Interrupt Enable 2D (CME2D): Enables or disables interrupt requests by CMF2D in TSR2B
when CMF2D is set to 1.
Bit 3: CME2D
0
1
Description
CMI2D interrupt requested by CMF2D is disabled
CMI2D interrupt requested by CMF2D is enabled
(Initial value)
• Bit 2—Compare-Match Interrupt Enable 2C (CME2C): Enables or disables interrupt requests by CMF2C in TSR2B
when CMF2C is set to 1.
Bit 2: CME2C
0
1
Description
CMI2C interrupt requested by CMF2C is disabled
CMI2C interrupt requested by CMF2C is enabled
(Initial value)
• Bit 1—Compare-Match Interrupt Enable 2B (CME2BB): Enables or disables interrupt requests by CMF2B in TSR2B
when CMF2B is set to 1.
Bit 1: CME2B
0
1
Description
CMI2B interrupt requested by CMF2B is disabled
CMI2B interrupt requested by CMF2B is enabled
(Initial value)
• Bit 0—Compare-Match Interrupt Enable 2A (CME2A): Enables or disables interrupt requests by CMF2A in TSR2B
when CMF2A is set to 1.
Bit 0: CME2A
0
1
Description
CMI2A interrupt requested by CMF2A is disabled
CMI2A interrupt requested by CMF2A is enabled
(Initial value)
Timer Interrupt Enable Register 3 (TIER3)
TIER3 controls enabling/disabling of channel 3 to 5 input capture, compare-match, and overflow interrupt requests.
Bit:
15
—
Initial value:
0
R/W:
R
14
OVE5
0
R/W
13
IME5D
0
R/W
12
IME5C
0
R/W
11
IME5B
0
R/W
10
IME5A
0
R/W
9
OVE4
0
R/W
8
IME4D
0
R/W
Bit:
Initial value:
R/W:
7
IME4C
0
R/W
6
IME4B
0
R/W
5
IME4A
0
R/W
4
OVE3
0
R/W
3
IME3D
0
R/W
2
IME3C
0
R/W
1
IME3B
0
R/W
0
IME3A
0
R/W
• Bit 15—Reserved: This bit is always read as 0. The write value should always be 0.
Rev.3.00 Mar. 12, 2008 Page 231 of 948
REJ09B0177-0300