SH7059 Datasheet, PDF (611/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Bit 1: ADSEL1B
0
1
Description
Conversion result is transferred to ADDR22
Conversion result is transferred to ADDR23
19. Multi-Trigger A/D Converter (MTAD)
(Initial value)
• Bit 1—A/D Data Select 0B (ADSEL0B): Selects the register to which the result of multi-trigger A/D conversion is
transferred.
This bit is inverted when the ADDR register is updated by the multi-trigger A/D conversion.
Switching settings during the multi-trigger A/D conversion operation should be carried out when TADF0B (ADTSR0
register) is set to 1.
Bit 1: ADSEL0B
0
1
Description
Conversion result is transferred to ADDR10
Conversion result is transferred to ADDR11
(Initial value)
• Bit 0—A/D Data Select 1A (ADSEL1A): Selects the register to which the result of multi-trigger A/D conversion is
transferred.
This bit is inverted when the ADDR register is updated by the multi-trigger A/D conversion.
Switching settings during the multi-trigger A/D conversion operation should be carried out when TADF1A (ADTSR1
register) is set to 1.
Bit 0: ADSEL1A
0
1
Description
Conversion result is transferred into ADDR20
Conversion result is transferred into ADDR21
(Initial value)
• Bit 0—A/D Data Select 0A (ADSEL0A): Selects the register to which the result of multi-trigger A/D conversion is
transferred.
This bit is inverted when the ADDR register is updated by the multi-trigger A/D conversion.
Switching settings during the multi-trigger A/D conversion operation should be carried out when TADF0A (ADTSR0
register) is set to 1.
Bit 0: ADSEL0A
0
1
Description
Conversion result is transferred to ADDR8
Conversion result is transferred to ADDR9
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 521 of 948
REJ09B0177-0300