SH7059 Datasheet, PDF (185/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Interrupt Controller (INTC)
If the necessary number of states is not secured after flag clear of the interrupt source, the interrupt may occur
again.
Interrupt acceptance
IRQ
IRQ synchronization
Interrupt controller operation
6 to 9
5 + m1 + m2 + m3
2
3 m1 m2 1 m3 1
Instruction (instruction
replaced by interrupt
exception processing)
F DE E MMEME E
Overrun fetch
F
Interrupt service routine
start instruction
FDE
Legend:
F: Instruction fetch (instruction fetched from memory where program is stored).
D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed
according to the results of decoding).
M: Memory access (data in memory is accessed).
Figure 7.4 Example of Pipeline Operation when an IRQ Interrupt is Accepted
Rev.3.00 Mar. 12, 2008 Page 95 of 948
REJ09B0177-0300