SH7059 Datasheet, PDF (742/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. ROM (SH7058S)
24.4.2 Programming/Erasing Interface Registers
The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in
bytes. These registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode.
(1) Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming
or erasing flash memory and the download of the on-chip program.
Bit :
7
6
5
4
3
2
1
0
FWE
—
—
FLER
—
—
—
SCO
Initial value : 1/0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
(R)W
• Bit 7—Flash Programming Enable (FWE): Monitors the level which is input to the FWE pin that performs hardware
protection of the flash memory programming or erasing. The initial value is 0 or 1 according to the FWE pin state.
Bit 7
FWE
Description
0
When the FWE pin goes low (in hardware protection state)
1
When the FWE pin goes high
• Bits 6 and 5—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 4—Flash Memory Error (FLER): Indicates an error occurs during programming and erasing flash memory.
When FLER is set to 1, flash memory enters the error protection state.
This bit is initialized at a power-on reset or in hardware standby mode.
When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the
reset signal must be released after the reset period of 100 μs which is longer than normal.
Bit 4
FLER
0
1
Description
Flash memory operates normally
Programming/erasing protection for flash memory (error protection) is invalid.
[Clearing condition] At a power-on reset or in hardware standby mode
Indicates an error occurs during programming/erasing flash memory.
Programming/erasing protection for flash memory (error protection) is valid.
[Setting condition] See section 24.6.3, Error Protection.
(Initial value)
• Bits 3 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 0—Source Program Copy Operation (SCO): Requests the on-chip programming/erasing program to be downloaded
to the on-chip RAM.
When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-
chip RAM area specified by FTDAR.
In order to set this bit to 1, RAM emulation state must be canceled, H'A5 must be written to FKEY, and this operation
must be in the on-chip RAM.
Eight NOP instructions must be executed immediately after setting this bit to 1.
Rev.3.00 Mar. 12, 2008 Page 652 of 948
REJ09B0177-0300