SH7059 Datasheet, PDF (658/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Advanced User Debugger (AUD)
21.3 Branch Trace Mode
21.3.1 Overview
In this mode, the branch destination address is output when a branch occurs in the user program. Branches may be caused
by branch instruction execution or interrupt/exception processing, but no distinction is made between the two in this mode.
21.3.2 Operation
Operation starts in branch trace mode when AUDRST is asserted, AUDMD is driven low, then AUDRST is negated*.
Figure 21.2 shows an example of data output.
While the user program is being executed without branches, the AUDATA pins constantly output 0011 in synchronization
with AUDCK.
When a branch occurs, after execution starts at the branch destination address in the PC, the previous fully output address
(i.e. for which output was not interrupted by the occurrence of another branch) is compared with the current branch
address, and depending on the result, AUDSYNC is asserted and the branch destination address is output after AUDCK-
based 1-clock output of 1000 (in the case of 4-bit output), 1001 (8-bit output), 1010 (16-bit output), or 1011 (32-bit output)
from the AUDATA pins.
On completion of the cycle in which the address is output, AUDSYNC is negated and 0011 is output from the AUDATA
pins.
If another branch occurs during branch destination address output, the later branch has priority for output. In this case,
AUDSYNC is negated and the AUDATA pins output the address after outputting 10xx again (figure 21.3 shows an
example of the output when consecutive branches occur). Note that the compared address is the previous fully output
address, and not an interrupted address (since the upper address of an interrupted address will be unknown).
The interval from the start of execution at the branch destination address in the PC until the AUDATA pins output 10xx is
1.5 or 2 AUDCK cycles.
Start of execution at branch destination address in PC
AUDCK
AUDATA [3:0] 0011 0011 1011 A3–A0 A7–A4 A11–A8 A15–A12 A19–A16 A23–A20 A27–A24 A31–A28 0011
Figure 21.2 Example of Data Output (32-Bit Output)*
Rev.3.00 Mar. 12, 2008 Page 568 of 948
REJ09B0177-0300