SH7059 Datasheet, PDF (160/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Exception Processing
6.3 Address Errors
6.3.1 Address Error Sources
Address errors occur when instructions are fetched or data read or written, as shown in table 6.6.
Table 6.6 Bus Cycles and Address Errors
Bus Cycle
Type
Bus Master
Bus Cycle Description
Address Errors
Instruction fetch CPU
Instruction fetched from even address
None (normal)
Instruction fetched from odd address
Address error occurs
Instruction fetched from other than on-chip peripheral None (normal)
module space*
Instruction fetched from on-chip peripheral module Address error occurs
space*
Instruction fetched from external memory space
when in single chip mode
Address error occurs
Data read/write CPU or DMAC Word data accessed from even address
None (normal)
Word data accessed from odd address
Address error occurs
Longword data accessed from a longword boundary None (normal)
Longword data accessed from other than a long-
word boundary
Address error occurs
Byte or word data accessed in on-chip peripheral
module space*
None (normal)
Longword data accessed in 16-bit on-chip peripheral None (normal)
module space*
Longword data accessed in 8-bit on-chip peripheral Address error occurs
module space*
External memory space accessed when in single
chip mode
Address error occurs
Note: * See section 9, Bus State Controller (BSC), for details of the on-chip peripheral module space.
6.3.2 Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then
finishes, address error exception processing starts up. The CPU operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be
executed after the last executed instruction.
3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the
address error that occurred and the program starts executing from that address. The jump that occurs is not a delayed
branch.
Rev.3.00 Mar. 12, 2008 Page 70 of 948
REJ09B0177-0300