SH7059 Datasheet, PDF (155/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Exception Processing
6. Exception Processing
6.1 Overview
6.1.1 Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority
shown in table 6.1. When several exception processing sources occur at once, they are processed according to the priority
shown.
Table 6.1 Types of Exception Processing and Priority Order
Exception
Source
Priority
Reset
Address error
Instructions
Interrupt
Instructions
Power-on reset
Manual reset
CPU address error
DMAC address error
FPU exception
NMI
User break
H-UDI
IRQ
On-chip peripheral modules:
• Direct memory access controller (DMAC)
• Advanced timer unit-II (ATU-II)
• Compare match timer 0 (CMT0)
• Multi trigger A/D0 (MTAD0)
• A/D converter channel 0 (A/D0)
• Compare match timer 1 (CMT1)
• Multi trigger A/D1 (MTAD1)
• A/D converter channel 1 (A/D1)
• A/D converter channel 2 (A/D2)
• Serial communication interface (SCI)
• Synchronous serial communication unit (SSU)
• Controller area network 0 (HCAN0)
• Watchdog timer (WDT)
• Controller area network 1 (HCAN 1)
Trap instruction (TRAPA instruction)
High
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay branch instruction*¹ or Low
instructions that rewrite the PC*²)
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF.
Rev.3.00 Mar. 12, 2008 Page 65 of 948
REJ09B0177-0300