SH7059 Datasheet, PDF (494/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
16.3.4 SS Enable Register (SSER)
SSER controls the transmit enable, receive enable, and interrupt request enable.
Bit:
7
6
5
4
3
2
1
0
TE
RE
—
—
TEIE
TIE
RIE
CEIE
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Bit Name
7 TE
6
RE
5, 4 ⎯
3 TEIE
2 TIE
1 RIE
0 CEIE
Initial Value R/W
0
R/W
0
R/W
All 0
⎯
0
R/W
0
R/W
0
R/W
0
R/W
Description
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Reserved
These bits are always read as 0. The write value should always be 0.
Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is enabled.
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI interrupt request and OEI interrupt request
are enabled.
Conflict Error Interrupt Enable
When this bit is set to 1, CEI interrupt request is enabled.
SSER is initialized to H'00 by a power-on reset and hardware standby mode. The value is not retained in software standby
mode and it is initialized after release. It is not initialized by a manual reset.
Rev.3.00 Mar. 12, 2008 Page 404 of 948
REJ09B0177-0300