SH7059 Datasheet, PDF (138/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
2.5 Processing States
2.5.1 State Transitions
The CPU has five processing states: power-on reset, exception processing, bus release, program execution and power-
down. Figure 2.8 shows the transitions between the states.
From any state
when RES = 0
and HSTBY = 1
Power-on reset state
When an interrupt source
or DMA address error occurs
RES = 1
Exception processing state
RES = 0
HSTBY = 1
NMI pin
0 →1
Bus request
cleared
Bus request
generated
Bus release state
Exception
processing
source occurs
Exception
processing
ends
Bus request
generated
Bus request
cleared
Bus request
generated
Bus request
cleared
SBY bit
cleared
for SLEEP
instruction
Program execution state
SBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Hardware standby mode
Power-down state
From any state when
RES = 0 and HSTBY = 0
Note: An internal reset due to the WDT causes a transition from the program execution state
or sleep mode to the exception processing state.
Figure 2.8 Transitions between Processing States
Rev.3.00 Mar. 12, 2008 Page 48 of 948
REJ09B0177-0300