SH7059 Datasheet, PDF (18/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
10.3.7 Relationship between Request Modes and Bus
Modes by DMA Transfer Category
190
1. Auto-request or on-chip peripheral module request
enabled. However, in the case of an on-chip peripheral
module request, it is not possible to specify the SCI,
HCAN0, or A/D converter for the transfer request source.
2. Auto-request or on-chip peripheral module request
possible. However, if the transfer request source is also the
SCI, HCAN0, or A/D converter, the transfer source or
transfer destination must be same as the transfer source.
3. When the transfer request source is the SCI, only
cycle-steal mode is possible.
10.3.7 Relationship between Request Modes and Bus
Modes by DMA Transfer Category
Note amended
1. Auto-request or on-chip peripheral module request
enabled. However, in the case of an on-chip peripheral
module request, it is not possible to specify the SCI,
HCAN0, SSU*⁵, or A/D converter for the transfer request
source.
2. Auto-request or on-chip peripheral module request
possible. However, if the transfer request source is also the
SCI, HCAN0, SSU*⁵, or A/D converter, the transfer source
or transfer destination must be same as the transfer
source.
3. When the transfer request source is the SCI, or SSU*⁵,
only cycle-steal mode is possible.
11.1.1 Features
Table 11.1 ATU-II Functions
202, 203
11.1.1 Features
Table 11.1 ATU-II Functions
Table amended
Item
Counter
Clock sources
configuration
Channel 0
φ−φ/32
Channel 1
Channel 2
Channels 3−5
(φ−φ/32) × (1/2n)
(n = 0−5)
TCLKA, TCLKB, AGCK,
AGCKM
(φ−φ/32) × (1/2n)
(n = 0−5)
TCLKA, TCLKB, AGCK,
AGCKM
(φ−φ/32) × (1/2n)
(n = 0−5)
TCLKA, TCLKB, AGCK,
AGCKM
Item
Counter
Clock sources
configuration
Channel 0
Pφ−Pφ/32
Channel 1
Channel 2
Channels 3−5
(Pφ−Pφ/32) × (1/2n)
(n = 0−5)
TCLKA, TCLKB, AGCK,
AGCKM
(Pφ−Pφ/32) × (1/2n)
(n = 0−5)
TCLKA, TCLKB, AGCK,
AGCKM
(Pφ−Pφ/32) × (1/2n)
(n = 0−5)
TCLKA, TCLKB, AGCK,
AGCKM
Item
Counter
configuration
Channels 6, 7
Clock sources (φ−φ/32) × (1/2n)
(n = 0−5)
Channel 8
(φ−φ/32) × (1/2n)
(n = 0−5)
Channel 9
⎯
Channel 10
(φ−φ/32)
Channels 11
(φ−φ/32) × (1/2n)
(n = 0−5)
TCLKA, TCLKB
11.1.6 Prescaler Diagram
Figure 11.12 Prescaler Diagram
229
Input clock φ/2
11.2.5 Timer Status Registers (TSR)
273
• Bit 3—Input Capture/Compare-Match Flag 3D (IMF3D):
Status flag that indicates GR5D input capture or
compare-match.
11.3.9 PWM Timer Function
Figure 11.21 PWM Timer Operation
375
Item
Counter
configuration
Channels 6, 7
Clock sources (Pφ−Pφ/32) × (1/2n)
(n = 0−5)
Channel 8
(Pφ−Pφ/32) × (1/2n)
(n = 0−5)
Channel 9
⎯
Channel 10
(Pφ−Pφ/32)
Channels 11
(Pφ−Pφ/32) × (1/2n)
(n = 0−5)
TCLKA, TCLKB
11.1.6 Prescaler Diagram
Figure 11.12 Prescaler Diagram
Figure amended
Input clock Pφ
11.2.5 Timer Status Registers (TSR)
Description amended
• Bit 3—Input Capture/Compare-Match Flag 3D (IMF3D):
Status flag that indicates GR3D input capture or
compare-match.
11.3.9 PWM Timer Function
Figure 11.21 PWM Timer Operation
Figure amended
Pφ
Pφ
STR
TCNT6A
Clock
TCNT6A 0001 0002 0003 0004 0003 0002 0001 0000 0001 0002 0003 0004 0003 0002 0001 0000 0001 0002 0003
CYLR6A
Write to
BFR6A
Data = 0000
0004
Data = 0004
Data = 0001
BFR6A
0002
0000
0004
0001
DTR6A
TO6A
*
PWM output does not change
for one cycle after activation
TSR6
CMF6A
Cycle
0002
0000
0004
0001
Cleared by software
Cleared by software
Cleared by software
Cycle
Cycle
Duty = 0%
Cycle
Duty = 100%
Cycle
Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation.
STR6A
TCNT6A
Clock
TCNT6A 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003
CYLR6A
Write to
BFR6A
Data = 0000
0004
Data = 0004
Data = 0001
BFR6A
0002
0000
0004
0001
DTR6A
TO6A
*
PWM output does not change
for one cycle after activation
TSR6
CMF6A
Cycle
0002
0000
0004
0001
Cleared by software
Cleared by software
Cleared by software
Cycle
Cycle
Duty = 0%
Cycle
Duty = 100%
Cycle
Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation.
Rev.3.00 Mar. 12, 2008 Page xviii of xc
REJ09B0177-0300