SH7059 Datasheet, PDF (902/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

26. RAM
26.2 Operation
The on-chip RAM is controlled by means of the system control register (SYSCR).
When the RAME bit in SYSCR is set to 1, the on-chip RAM is enabled. Addresses H'FFFF0000 to H'FFFFBFFF in the
SH7058S or H'FFFE8000 to H'FFFFBFFF in the SH7059 then provide access to the on-chip RAM.
When the RAME bit in SYSCR is cleared to 0, the on-chip RAM is not accessed. A read will return an undefined value,
and a write is invalid. If a transition is made to hardware standby mode after the RAME bit in SYSCR is cleared to 0, the
contents of the on-chip RAM are held.
For details of SYSCR, see section 27.2.2, System Control Register1 (SYSCR1), in section 27, Power-Down State.
Rev.3.00 Mar. 12, 2008 Page 812 of 948
REJ09B0177-0300