SH7059 Datasheet, PDF (901/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 26 RAM
26. RAM
26.1 Overview
The SH7058S and SH7059 have 48 and 80 Kbytes of on-chip RAM, respectively. The on-chip RAM is linked to the CPU,
direct memory access controller (DMAC), and advanced user debugger (AUD) with a 32-bit data bus (figure 26.1).
The CPU, DMAC, and AUD can access data in the on-chip RAM in 8, 16, or 32 bit widths. On-chip RAM data can
always be accessed in one cycle for a read and two states for a write, making the RAM ideal for use as a program area,
stack area, or data area, which require high-speed access. The contents of the on-chip RAM are held in both the sleep and
software standby modes. When the RAME bit (see below) is cleared to 0, the on-chip RAM contents are also held in
hardware standby mode.
The on-chip RAM is allocated to addresses H'FFFF0000 to H'FFFFBFFF in the SH7058S and H'FFFE8000 to
H'FFFFBFFF in the SH7059.
SH7058S
8
bits
H'FFFF0000
H'FFFF0004
Internal data bus (32 bits)
8
8
bits
bits
H'FFFF0001
H'FFFF0005
H'FFFF0002
H'FFFF0006
8
bits
H'FFFF0003
H'FFFF0007
On-chip RAM
H'FFFFBFFC H'FFFFBFFD H'FFFFBFFE H'FFFFBFFF
SH7059
8
bits
H'FFFE8000
H'FFFE8004
Internal data bus (32 bits)
8
8
bits
bits
H'FFFE8001
H'FFFE8005
H'FFFE8002
H'FFFE8006
8
bits
H'FFFE8003
H'FFFE8007
On-chip RAM
H'FFFFBFFC H'FFFFBFFD H'FFFFBFFE H'FFFFBFFF
Figure 26.1 Block Diagram of RAM
Rev.3.00 Mar. 12, 2008 Page 811 of 948
REJ09B0177-0300