SH7059 Datasheet, PDF (302/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 0—Compare-Match Flag 2A (CMF2A): Status flag that indicates OCR2A compare-match.
Bit 0: CMF2A
0
1
Description
[Clearing condition]
When CMF2A is read while set to 1, then 0 is written to CMF2A
[Setting condition]
When TCNT2B = OCR2A
(Initial value)
Timer Status Register 3 (TSR3)
TSR3 indicates the status of channel 3 to 5 input capture, compare-match, and overflow.
Bit:
15
14
13
12
11
10
—
OVF5
IMF5D
IMF5C
IMF5B
IMF5A
Initial value:
0
0
0
0
0
0
R/W:
R
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
9
OVF4
0
R/(W)*
8
IMF4D
0
R/(W)*
Bit:
Initial value:
R/W:
7
IMF4C
0
R/(W)*
6
IMF4B
0
R/(W)*
5
IMF4A
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
4
OVF3
0
R/(W)*
3
IMF3D
0
R/(W)*
2
IMF3C
0
R/(W)*
1
IMF3B
0
R/(W)*
0
IMF3A
0
R/(W)*
• Bit 15—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 14—Overflow Flag 5 (OVF5): Status flag that indicates TCNT5 overflow.
Bit 14: OVF5
0
1
Description
[Clearing condition]
When OVF5 is read while set to 1, then 0 is written to OVF5
[Setting condition]
When the TCNT5 value overflows (from H'FFFF to H'0000)
(Initial value)
• Bit 13—Input Capture/Compare-Match Flag 5D (IMF5D): Status flag that indicates GR5D input capture or compare-
match.
Bit 13: IMF5D
0
1
Description
[Clearing condition]
When IMF5D is read while set to 1, then 0 is written to IMF5D
(Initial value)
[Setting conditions]
• When the TCNT5 value is transferred to GR5D by an input capture signal while GR5D is
functioning as an input capture register
• When TCNT5 = GR5D while GR5D is functioning as an output compare register
• When TCNT5 = GR5D while GR5D is functioning as a cycle register in PWM mode
Rev.3.00 Mar. 12, 2008 Page 212 of 948
REJ09B0177-0300