SH7059 Datasheet, PDF (20/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
13.2.2 Timer Control/Status Register (TCSR)
441
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0)
13.2.2 Timer Control/Status Register (TCSR)
Table amended
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0)
Description
Description
Overflow Interval*
(φ = 40 MHz)
12.8 µs
409.6 µs
0.8 ms
1.6 ms
3.3 ms
6.6 ms
26.2 ms
52.4 ms
Note: * The overflow interval listed is the time from when
the TCNT begins counting at H'00 until an overflow occurs.
Refer to section 13.4.7, Multiplication Factor for Internal
Clock Signal (φ) and Overflow Time.
Overflow Interval* (φ = 80 MHz)
6.4 µs
204.8 µs
409.6 µs
0.8 ms
1.6 ms
3.3 ms
13.1 ms
26.2 ms
Note amended
Note: * The overflow interval listed is the time from when
the TCNT begins counting at H'00 until an overflow occurs.
.
13.4.7 Multiplication Factor for Internal Clock Signal (φ) and 13.4.7 Multiplication Factor for Internal Clock Signal (φ) and
Overflow Time
Overflow Time
449
Deleted
14.1.3 Register Configuration
Table 14.1 Register Configuration
453
Notes: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles for
byte access and word access, and eight or nine internal
clock (φ) cycles for longword access.
* Only 0 can be written to the CMCSR0 and CMCSR1 CMF
bits to clear the flags.
14.1.3 Register Configuration
Table 14.1 Register Configuration
Note amended
Notes: * Only 0 can be written to the CMCSR0 and
CMCSR1 CMF bits to clear the flags.
15.1.4 Register Configuration
Table 15.2 Register
467
Notes: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles for
byte access and word access, and eight or nine internal
clock (φ) cycles for longword access.
1. Only 0 can be written to clear the flags.
2. Do not access empty addresses.
15.1.4 Register Configuration
Table 15.2 Register
Note amended
Notes: *1 Only 0 can be written to clear the flags.
*2 Do not access empty addresses.
15.2.5 Serial Mode Register (SMR)
469
The CPU can always read and write to SMR. SMR is
initialized to H'00 by a power-on reset and in hardware
standby mode. It is not initialized by a manual reset and in
software standby mode.
15.2.5 Serial Mode Register (SMR)
Description amended
The CPU can always read to SMR. The CPU should only
perform write operations when making initial settings. Do
not use the CPU to perform writes during transmit, receive,
or transmit/receive operation. SMR is initialized to H'00 by
a power-on reset, in hardware standby mode. The value is
not retrained in software standby mode and it is initialized
after release. It is not initialized by a manual reset.
Rev.3.00 Mar. 12, 2008 Page xx of xc
REJ09B0177-0300