SH7059 Datasheet, PDF (507/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
Start
[1]
Initialization
[2]
Read TDRE in SSSR.
No
TDRE = 1?
Yes
Write transmit data to SSTDR
TDRE automatically cleared to 0
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
[3]
No
Read SSSR
RDRF = 1?
Yes
ORER = 1?
No
Read received data in SSRDR
Yes [4]
RDRF automatically cleared to 0
Continuous data
transmission/reception
No
Yes [5]
[1] Initialization:
Specify the settings such as transmit/receive
data format
[2] Check the SSU state and write transmit data
Write transmit data to SSTDR after reading SSSR
and confirming that the TDRE bit is 1. The TDRE
bit is automatically cleared to 0 by writing data to
SSTDR. Data transmission or reception is started
by writing data to SSTDR.
[3] Check the SSU state and read receive data:
Read receive data in SSRDR after reading and
confirming that the RDRF bit is 1. A change of the
RDRF bit (from 0 to 1) can be notified by RXI
interrupt.
[4] Receive error processing:
When a receive error occurs, read the ORER bit in
SSSR and then execute the designated error
processing. After that, clear the ORER bit to 0.
While the ORER bit is set to 1, transmission or
reception is not resumed.
[5] Procedure for continuous data transmission/
reception:
To continue setial data transmission/reception,
confirm that the TDRE bit 1meaning that SSTDR
is ready to be written to. After that, data can be
written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
Read TEND in SSSR
TEND = 1 ?
No
Yes
Clear TEND in SSSR to 0
Error processing
1-bit duration elapsed ?
No
Yes
Clear TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Figure 16.9 Example of Simultaneous Transmission/Reception Flowchart
Rev.3.00 Mar. 12, 2008 Page 417 of 948
REJ09B0177-0300