SH7059 Datasheet, PDF (545/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Bit
Bit Name Initial Value R/W Description
15 to 0 TXCR1[15:0] 0
R/W* Request the corresponding mailbox, that is in the queue for transmission, to
cancel its transmission wait. Bits 15 to 0 correspond to mailboxes 31 to 16
and TXPR1[15:0] respectively.
0: Corresponding mailbox is in transmit message cancellation idle state
Clearing condition: Completion of transmit wait cancellation (automatically
cleared)
1: Transmit wait cancellation request made for corresponding mailbox
Note: * 1 can be written only to a mailbox that is requested for transmission or set for transmission.
• TXCR0n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCR0[15:1]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R
Bit
Bit Name Initial Value R/W Description
15 to 1 TXCR0[15:1] 0
R/W* Request the corresponding mailbox, that is in the queue for transmission, to
cancel its transmission wait. Bits 15 to 1 correspond to mailboxes 15 to 1
and TXPR0[15:1] respectively.
0: Corresponding mailbox is in transmit message cancellation idle state
Clearing condition: Completion of transmit wait cancellation (automatically
cleared)
1: Transmit wait cancellation request made for corresponding mailbox
0
⎯
0
R
Reserved
This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is
ignored. The read value is always 0.
Note: * 1 can be written only to a mailbox that is requested for transmission or set for transmission.
17.5.3 Transmit Acknowledge Register n (TXACK1n, TXACK0n) (n = 0, 1)
TXACK1 and TXACK0 are 16-bit readable/conditionally-writable registers. These registers notify the host CPU that a
mailbox transmission has been successfully made. When a transmission has succeeded, the HCAN sets the corresponding
bit in TXACK. The host CPU can clear a TXACK bit by writing 1 to the corresponding bit. Writing 0 is ignored.
• TXACK1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXACK1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R / R / R / R / R / R / R / R / R / R / R / R / R / R / R / R /
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Rev.3.00 Mar. 12, 2008 Page 455 of 948
REJ09B0177-0300