SH7059 Datasheet, PDF (614/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Multi-Trigger A/D Converter (MTAD)
19.2.3 A/D Trigger Interrupt Enable Registers 0 and 1 (ADTIER0 and ADTIER1)
A/D trigger interrupt enable registers 0 and 1 (ADTIER0 and ADTIER1) enable or disable interrupt request triggered by
the compare match generation and multi-trigger A/D conversion end in channels 0 and 1.
ADTIER0 and ADTIER1 are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby
mode.
Bit:
Initial value:
R/W:
7
ADTRGx
0
R/W
6
TADExB
0
R/W
5
TADExA
0
R/W
4
ADDExB
0
R/W
3
ADDExA
0
R/W
2
1
0
ADCYLFx ADCMExB ADCMExA
0
0
0
R/W
R/W
R/W
Note: x = 0 or 1.
• Bit 7—ADT Trigger (ADTRGx): Enables or disables triggering of multi-trigger A/D conversion by a compare match
between ADCNTx and ADGRxA or ADGRxB.
To prevent incorrect operation, ensure that the ADST bit in A/D control register (ADCR) is 0 before switching this
setting.
Bit 7: ADTRGx
Description
0
Triggering of multi-trigger A/D conversion by a compare match between ADCNTx and
ADGRxA or ADGRxB is disabled
(Initial value)
1
Triggering of multi-trigger A/D conversion by a compare match between ADCNTx and
ADGRxA or ADGRxB is enabled
Notes: 1. x = 0 or 1.
2. Value 1 can be set to ADTRGx only for the cases below; 0 should always be set for the other cases.
Conversion mode (ADCR): continuous scan
Channels for conversion (ADCSRx):
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADM1
ADM0
CH3
CH2
CH1
CH0
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
1
1
Notes: 1. x = 0 or 1.
2. For the ADCR and ADCSRx settings, refer to section 18, A/D Converter.
Analog Input Channels
A/D0
A/D1
AN0 to AN3 AN12 to AN15
AN0 to AN7 AN12 to AN19
AN4 to AN7 AN16 to AN19
• Bit 6—Trigger A/D Interrupt Enable B (TADExB): Enables or disables the interrupt request by TADFxB when the
trigger A/D flag xB (TADFxB) in ADTSR is set to 1.
To prevent incorrect operation, ensure that the ADTRG bit in A/D trigger interrupt enable register (ADTIER0 or
ADTIER1) is 0 before switching this setting.
Bit 6: TADExB
0
1
Description
The interrupt request (TADIxB) by TADFxB is disabled
The interrupt request (TADIxB) by TADFxB is enabled
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 524 of 948
REJ09B0177-0300