SH7059 Datasheet, PDF (477/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
15.3.4 Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for
high-speed serial communication.
The SCI transmitter and receiver are independent, so full duplex communication is possible while sharing the same clock.
The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or
writing data while transmitting or receiving is in progress.
Figure 15.16 shows the general format in synchronous serial communication.
Transfer direction
One unit (character or frame) of communication data
*
*
Serial clock
Serial data
LSB
MSB
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Note: * High except in continuous transmitting or receiving.
Figure 15.16 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial
clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are
transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in
the state of the MSB. In synchronous mode, the SCI transmits or receives data by synchronizing with the rise of the serial
clock.
Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be
selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR)
and bits CKE1 and CKE0 in the serial control register (SCR). See table 15.9.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per
transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state.
An overrun error occurs only during the receive operation, and the serial clock is output until the RE bit is cleared to 0. To
perform a receive operation in one-character units, select an external clock for the clock source.
Transmitting and Receiving Data
SCI Initialization (Synchronous Mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in
the serial control register (SCR), then initialize the SCI as follows.
When changing the mode or communication format, always clear the TE and RE bits to 0 before following the procedure
given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however,
does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous
contents.
Figure 15.17 is a sample flowchart for initializing the SCI.
Rev.3.00 Mar. 12, 2008 Page 387 of 948
REJ09B0177-0300