SH7059 Datasheet, PDF (206/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle between cycles for CS2
space; IW11, IW10 specify the idle between cycles for CS1 space and IW01, IW00 specify the idle between cycles for
CS0 space.
Bit 15: IW31
0
1
Bit 14: IW30
0
1
0
1
Description
No CS3 space idle cycle
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(Initial value)
Bit 13: IW21
0
1
Bit 12: IW20
0
1
0
1
Description
No CS2 space idle cycle
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(Initial value)
Bit 11: IW11
0
1
Bit 10: IW10
0
1
0
1
Description
No CS1 space idle cycle
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(Initial value)
Bit 9: IW01
0
1
Bit 8: IW00
0
1
0
1
Description
No CS0 space idle cycle
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(Initial value)
• Bits 7–4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle
specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when performing
consecutive accesses to the same CS space. When a write immediately follows a read, the number of idle cycles
inserted is the larger of the two values specified by IW and CW. Refer to section 9.4, Waits between Access Cycles,
for details.
CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access idles for CS2 space;
CW1 specifies the continuous access idles for CS1 space and CW0 specifies the continuous access idles for CS0 space.
Bit 7: CW3
0
1
Description
No CS3 space continuous access idle cycles
One CS3 space continuous access idle cycle
(Initial value)
Bit 6: CW2
0
1
Description
No CS2 space continuous access idle cycles
One CS2 space continuous access idle cycle
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 116 of 948
REJ09B0177-0300